1. Field of the Invention
The present invention relates to an address decoder of a semiconductor memory, and particularly to a structure of an address decoder for a CMOS type dynamic RAM having static column function.
2. Description of the Prior Art
An address decoder for selecting one memory cell from a memory cell array included in a semiconductor memory is formed of a plurality of transistors, which are connected in series or in parallel and are switch-controlled by address signals.
Recently, a semiconductor memory has come to be implemented in a large capacity, increasing the number of bits required for address signals, so that the number of transistors forming an address decoder must be increased correspondingly. This increases the load capacitance of an address signal line, so that the speed of operation of an address decoder is greatly limited. On the other hand, this increases the area of device region required for forming an address decoder on a semiconductor chip.
In order to solve the above described problems, an address.predecoding method such as shown in, e.g. Japanese Patent Laying-Open Gazette No. 3289/1982 has been proposed.
FIG. 1 shows one example of a structure of a conventional address decoder according to the address predecoding method. In FIG. 1, a conventional address decoder comprises an address buffer circuit 1 for receiving an externally applied address input signals Ext. Ai (i=0,1,...,5) to output the complementary address signal Ai, Ai a predecoder circuit 2 composed of four 2-input NAND gates for receiving and predecoding address signals A.sub.2j, A.sub.2j, A.sub.2j+1, and A.sub.2j+1, from corresponding two address buffer circuits 1 to output intermediate signals Z.sub.4j, Z.sub.4j+1, Z.sub.4j+2 and Z.sub.4j+3 and, an NAND type unit decoder 3 composed of three parallel-connected p channel MOS transistors P.sub.11 .about.P.sub.13 and three series-connected n channel MOS transistors N.sub.11 .about.N.sub.13 for receiving and decoding a part of the intermediate signals from all of the predecoder circuits 2 to output a selection signal S.sub.k (k=0,...,63). V.sub.CC denotes the positive supply potential and V.sub.SS denotes the negative supply potential.
The operation will now be described with reference to FIG. 1. The address buffer circuit 1 receives an external address input signal Ext.Ai and applies complementary address signals Ai, Ai to the predecoder circuit 2. The predecoder circuit 2 receives the address signals A.sub.2j, A.sub.2j, A.sub.2j+1 and A.sub.2j+1 and outputs the intermediate signals Z.sub.4j, Z.sub.4j+1, Z.sub.4j+2, and Z.sub.4j+3 which satisfy the following equations (1).about.(4). EQU Z.sub.4j =A.sub.2j .multidot.A.sub.2j+1 ( 1) EQU Z.sub.4j+1 =A.sub.2j .multidot.A.sub.2j+1 ( 2) EQU Z.sub.4j+2 =A.sub.2j .multidot.A.sub.2j+1 ( 3) EQU Z.sub.4j+3 =A.sub.2j .multidot.A.sub.2j+1 ( 4)
where, j =0, 1, 2.
The unit decoder 3 receives a predetermined part of the intermediate signals Z.sub.0 .about.Z.sub.11 from the predecoder circuit 2 (one from each of the predecoder circuits, i.e.; three signals in total) evaluates the negative logical product thereof and outputs a selection signal S.sub.k (k=0, ...63). For example, a unit decoder receiving the intermediate signals Z.sub.0, Z.sub.4 and Z.sub.8 outputs a selection signal S.sub.0 through the operation shown by the following equation (5). ##EQU1##
Accordingly, when the address signals A.sub.0 .about.A.sub.5 are all "L", the selection signal S.sub.0 becomes "L" and a signal line connected to the unit decoder output is selected.
FIG. 2 shows another structure of a conventional address decoder according to the predecoding method.
Different from the structure of FIG. 1, the predecoder circuit 4 for receiving and predecoding the address signals A.sub.2j, A.sub.2j, a.sub.2j+1 and A.sub.2j+1 (j=0,1,2) to output an intermediate signal is composed of four 2-input NAND gates in the structure of FIG. 2. The unit decoder 5 for receiving and decoding a predetermined set of three intermediate signals from all intermediate signals to output a selection signal is composed of a 3-inputs and 1-output NOR circuit comprising three series-connected p channel MOS transistors and three parallel-connected n channel MOS transistors. Namely, in this structure, the predecoder circuit 4 outputs active low intermediate signals Z.sub.4j, Z.sub.4j+1, Z.sub.4j+2, and Z.sub.4j+3. On the other hand, the NOR type unit decoder 5 outputs an active high selection signal S.sub.k (k=0,...63) in response to the applied intermediate signal.
The operation will now be described with reference to FIG. 2.
The predecoder circuit 4 receives the address signals A.sub.j, A.sub.j, A.sub.j+1 and A.sub.j+1 from the address buffer circuit 1, evaluates respective negative logical products and outputs intermediate signals Z.sub.4j, Z.sub.4j+1, Z.sub.4j+2 and Z.sub.4j+3 which satisfy the following equations (6).about.(9). EQU Z.sub.4j =A.sub.2j .multidot.A.sub.2j+1 =A.sub.2j +A.sub.2j+1 ( 6) EQU Z.sub.4j+1 =A.sub.2j .multidot.A.sub.2j+1 =A.sub.2j +A.sub.2j+1 ( 7) EQU Z.sub.4j+2 =A.sub.2j .multidot.A.sub.2j+1 =A.sub.2j +A.sub.2j+1 ( 8) EQU Z.sub.4j+3 =A.sub.2j .multidot.A.sub.2j+1 =A.sub.2j +A.sub.2j+1 ( 9)
where, j=0, 1, 2.
The unit decoder 5 receives one predetermined intermediate signal from each of the predecoder circuits 4 (three intermediate signals in total), evaluates negative logic sum thereof and outputs a selection signal S.sub.k (k=0, . . . 63). For example, a unit decoder receiving intermediate signals Z.sub.0, Z.sub.4, and Z.sub.8 outputs a selection signal S.sub.0 which satisfies the following equation (10). ##EQU2## Therefore, when address signals A.sub.1 .about.A.sub.5 are all "L", this unit decoder only is selected and the selection signal S.sub.0 becomes "H". Accordingly, only the signal line for receiving the selection signal S.sub.0 is selected.
As described above with reference to FIGS. 1 and 2, in an address decoder using the predecoding method, a unit decoder for decoding 6-bit address information A.sub.0 .about.A.sub.6 is composed of a 3-input NAND circuit or 3-input NOR circuit. If the predecoding method is not used, a unit decoder for decoding the 6-bit address informtion must be composed of 6-input NAND or NOR circuit. Accordingly, by employing the predecoding mehtod, the number of elements required for composing a unit decoder can be decreased to 1/2. Consequently, the number of element connected to the address information line becomes a half, so that the load capacitance on the address information line is greatly decreased, enabling the rapid operation of address decoding. In addition, due to the decrease of the number of elements the areas of element region forming the address decoder can be reduced.
However, in the conventional predecoding method, if the unit decoder is composed of a NAND circuit, the predecoder must output NOR outputs (i.e., active-high signal) and if the unit decoder is an NOR circuit, the predecoder must output NAND outputs (i.e., active-low signal) due to the above described circuit structure.
Recently, a DRAM (dynamic random access memory) having static column function has becn developed in order to improve the access time of a semiconductor memory. Details of the static column function is disclosed in F. Baba et al., "A 35 ms 64k Static Column DRAM", ISSCC Digest of Technical Papers, Feb. 1983, pp.64-65 and F. Baba et al., Nikkei Electronics 1983, vol. 9-12, pp. 153-174. Therefore, the description is omitted.
In the CMOS type DRAM having static column function, the column decoder and not the row decoder requires the static operation. Therefore, in view of the rapidity of the decoder and the number of elements forming the decoder, a combination of a row decoder formed of nMOS dynamic NOR circuits and column decoder composed of CMOS static NAND circuits is most preferable. However, as described above, in order to form a decoder employing the combination of an NOR type row decoder and an NAND type column decoder, a predecoder must be provided for each of the row address and the column address. Alternatively, in order to use the predecoder both for the row address and the column address, the row decoder and the column decoder must be composed of circuits of the same type. Therefore, in either case, a decoder cannot be constructed in its most suitable way in view of its performance or the number of elements for composing the circuit.
An address decoder using the predecoding method with an address decoder for one axis composed of an NAND circuit and an address decoder for the other axis composed of an NOR circuit is disclosed in U.S. Pat. No. 4,429,374 "Memory Array Addressing" by Tanimura.